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ISE Design Suite 13.1
FPGA Editor
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New Lock Layers toolbar button, which locks the current layer visibility settings for
all zoom levels.
iMPACT
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New SPI/BPI programming support:
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Numonyx P30 bottom boot is supported, in addition to top boot.
Winbond W25Q is supported up to 128Mb.
Winbond W25Q support for the CV revision has been added.
ChipScope Pro
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ChipScope Pro HDL (VHDL and Verilog) Debug probe using PlanAhead and XST
Synthesis flow
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Enable users to mark debug nets on HDL or XCF constraint file
When MARK_DEBUG attribute is used:
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Nets are preserved (not optimized away)
Nets appear in the ChipScope view in the PlanAhead view so users can
assign to debug cores
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ChipScope Pro HDL Debug probe using PlanAhead and Synplify Synthesis flow
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Enable users to mark debug nets on HDL (VHDL and Verilog) or SDC
When MARK_DEBUG attribute is used:
-
-
Nets are preserved (not optimized away)
Nets appear in the ChipScope view in the PlanAhead view so users can
assign to debug cores
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BERT for Virtex?-6 GTX and GTH available in PlanAhead and ChipScope Flow
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Also added low- and mid-range line rate support for IBERT V6 GTH
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Startup Trigger Mode
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Using Project Navigator, Core Inserter, and Analyzer Tools
Using PlanAhead software and Analyzer Tools
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BERT sweep test plot GUI
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Built-in graphical viewer of IBERT sweep test results for Virtex?-6 GTX/GTH
FPGA transceivers
Standalone graphical viewer for offline analysis of IBERT sweep test results for
Virtex?-6 FPGA GTX/GTH, Spartan?-6 FPGA GTP, and Virtex?-5 FPGA GTX
transceivers
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Tutorials:
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PlanAhead Tutorial: Debugging with ChipScope Analysis
ChipScope IBERT: Basic IBERT design flow
ISE Simulator
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Supports simulation of AXI BFM
Relaunch of simulation from the ISIM GUI
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
www.xilinx.com
19
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